In the last two decades, many efficient algorithms and architectures have been introduced for the design of low complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low complexity MCM operations albeit at the cost of an increased delay. In this paper the design of a digital-serial N tap FIR filter with programmable coefficients is presented. The design considers the general case of W-bit sample word and M-bit coefficient word. The processing of the data within the filter takes place with full precision. The output data is truncated to W bits. also in this paper we address the problem of optimizing the gate-level area in digit-serial MCM designs and introduce high level synthesis algorithms, design architectures, and a computer aided design tool.
IJCR is following an instant policy on rejection those received papers with plagiarism rate of more than 20%. So, All of authors and contributors must check their papers before submission to making assurance of following our anti-plagiarism policies.
