Design multiple value logic for full adder

Many developers have intended their models in binary and quaternary logic using 0.18µm CMOS technology. In Binary logic, circuit has limitations of increase interconnections giving rise to complexities and their by impact on size. Some authors concentrated on put back in place of binary logic with MVL or quaternary logic to prevail over the limitation of size. Second is that for half and full adder (for addition/ arithmetic operations) the quaternary logic method required the conversion of quaternary logic level into binary level for implementation. Our aim is to intend and develop MVL or quaternary logic for full adder without converting these levels to binary logic. It will reduce the one additional step and improve the performance offer less chip size, saving more power. MVL or quaternary logic can be implemented in three different modes. From that mode, voltage mode type model is beneficial to design and give high performance with less dynamic power dissipation. The design is targeted for the 0.18 μm CMOS technology. Design tool for simulation will be ADS [ADVANCED DESIGN SYSTEM] software. We will estimate area, power and delay of the design HAq / FAq without any need of conversion, and compare to existing binary circuits [HAb / FAb].