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Enhancing test pattern compaction algorithms for simple two stage circuits

Author: 
Thamarai, S.M., Kuppusamy, K. and Meyyappan, T
Subject Area: 
Physical Sciences and Engineering
Abstract: 

In this paper, a test pattern compaction algorithms for simple combinational circuits is proposed. It generates test pattern and simulate faults. Fault diagnosis is an important part of failure analysis. The fault diagnosis procedure considered here selects a set of faults and a set of tests. It stores fault simulation results in a fault dictionary and compares dictionary entries against observed faulty behaviors. It adopts fault based test minimization for simple two stage combinational circuits. Proposed Algorithm minimizes the number of test cases based on the number of faults detected. The problem of finding faults and diagnosis consists of two sub problems. The first problem is the determination of possible list of faults. It may include all possible single faults and multiple faults that may occur in a circuit. The second sub problem is minimizing number of tests to be performed to cover all the faults. The job of the proposed algorithm is to find essential tests from all possible test cases. The algorithm is implemented and sample boolean expressions in sum of product forms for sample circuits are experimented. The results obtained are tabulated and plotted. The time and space complexity of the algorithm are measured. From the results, it is observed that the execution time of the algorithm is linear. It increases with the increase in the number of gates in the given circuit. Test reduction upto 99% is observed. The performance of the proposed algorithm is compared with adaptive scheduled fault detection method, and found to be better in terms of reduction in number of tests and processor time it consumes.

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