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An efficient error detection and correction technique for memories using mldd

Author: 
An efficient error detection and correction technique for memories using mldd
Subject Area: 
Physical Sciences and Engineering
Abstract: 

Memory is an important component of an embedded system. Memory testing is very complex. Large error rates are occurring because of technology scaling and also due to higher integration densities. Soft errors are considered as one of the problems with respect to the memories. This paper focuses on the design of an efficient system, that detects and corrects the error. Hence, the number of cycles required to detect and correct the error is also less. EG-LDPC codes, that is, Euclidean Geometry Low Density Parity Check codes are used here. Previous method like Majority Logic Decoding requires more number of cycles for detection and correction of error. But, this paper deals about Majority Logic Detector/Decoder (MLDD) technique wherein error detection and correction takes place in less number of cycles. Hence, the speed of operation can be increased, power consumption can be reduced and also area required for this technique is very less.

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