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Fpga implementation of enhanced sha-192 algorithm

Author: 
Shiva Nagender Rao, L., Sai Rishishwar Reddy, Y. and Manoj Yasaswi, V.
Subject Area: 
Physical Sciences and Engineering
Abstract: 

Hash functions were introduced in Cryptology as a tool to protect the integrity of information. Secure Hash Algorithm-1 (SHA-1) and Message Digest-5 (MD-5) are among the most commonly used hash function message digest algorithms. Scientists have found collision attacks on SHA-1, MD-5 hash functions so the natural response to overcome this threat was assessing the weak points of these protocols that actually depend on collision resistance for their security. So to increase the security, modified SHA-192 is introduced in this paper having a message digest of length 192 bits with larger bit difference. To generate larger bit difference, best properties of MD-5andSHA-1 are combined. So the new solution will be no longer vulnerable to the collision attacks.SHA-192 currently used in security applications and protocols applications including Transport Layer Security (TLS), Secure Socket Layer (SSL), Internet Protocol Security (IPSec) and as Digital Signatures. This technique is designed by using Verilog HDL with Xilinx ISE Design suite 12.4 version tool. The designs implemented in Xilinx SPARTAN 3E XC3S500EFG320 FPGA board.

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