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Multi channel multi clock frequency speed rate real time industrial standard parallel prbs cdma transceiver array asic soc card design for ultra high speed wireless communication products/application cards

Author: 
Sastry, P. N. V. M. S. and Dr. D. N. Rao Dr. Vathsal
Subject Area: 
Physical Sciences and Engineering
Abstract: 

The Aim is for HDL Design Architecture and Implementation of Multi clock frequency synchronized real time industrial standard parallel Hi-tech PRBS CDMA Transceiver Bus Array ASIC SOC /Card for Ultra high Speed real time Industrial Communication Interface Cards/Products like Data Acquisition and Tracking of wireless Data Communication Protocol Interface Cards/SOC’s like Data Serializer, De-serializer, Data Communication Protocol interface ADD on cards/Products, FPGA Cards of Different Data Transfer Baud rate. This Design Consists of multiple parallel C.D.M.A Transmitters and Receiver ASIC I.P Cores, Data Transmission and Reception done by Different Clock Frequencies operated at Mega/Giga / Tera/ Peta/Exa/Zetta/Yotta/Xona/Weka Clock Frequencies. Data Transmission Speed In terms Mega/Giga/Tera/Peta/Exa/Zetta/Yotta/Xona/Weka Bytes/Frames/Super Frames etc. and also Data transmitter and receiver consists of base band signal and Carrier signal generators, Channel Encoder, Decoder, Modulator and Demodulator generates modulation and Demodulation signal by spreading and dispreading through different communication frequency spread Spectrum techniques DSSS Communication, FH , Chaos for high Bandwidth, the design done through parallel distributed computing technique, data transmission and reception done parallel for various data interface cards of different data transfer speed. In this design transmission and reception done by different PRBS Data Pattern Sequences like 2e7-1, 2e10-1, 2e15-1, 2e23-1, 2e31-1, 2e48-1, 2e52-1, 2e63-1 etc. H.D.L FPGA Industrial Software Design Flow Process Implementation Done by either Xilinx/Altera. Programming Done by Verilog /VHDL Software and Simulation, Synthesis, ASIC Floor planning and Placement and routing, Reconfiguration and Debugging Done Xilinx ISE 9.2i/10.1i EDA Software and Xilinx /Altera FPGA Development Board/Kit.

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