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Design of reduced loss 5*32 decoder using reversible gates

Author:

Mohan Rao Thokala

Subject Area:

Physical Sciences and Engineering

Abstract:

Reversible logic gates, in which the number of outputs is equal to number of inputs and each input, must give equal output pattern. These gates are reversible gates as it also helps in recovering inputs from outputs. The reversible 5x32 decoder consists of a reversible 4x16 decoder and fredk in gate which again consists of peres gate,one TR gate,one NOT gate, three CNOT gates,28 Fredkin gates. Reversible decoder 5x32 is designed with 4x16 decoder and fredkin gate with minimum cost, both delay and power consumption are reduced compared to normal decoder. Reversible decoder can be widely used in low power VLSI, DSP, nano computing, and optical computing.

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