Design and implementation of high speed optimized sdram controller based on FPGA for PCI interface

These days the requirement of memory is increasing day by day as it has become one of the integral part of the our day to day equipment’s that we use such as phones, computers, etc. the main reason for the popularity is its upgraded features like high speed of operation, easy to configure, very small in size and hence occupy negligible area, improved latency, and high performance. It has become possible due to advance controller that is used these days to provide necessary signal and commands to the SDRAM to perform at its best and provide outstanding features for the users. Hence it is very much necessary to design a controller for the SDRAM memory element to enhance its functionality. The paper proposed here basically targets the design and implementation of SDRAM controller to be designed for high speed interface with PCI Bus that can handle huge amount of data and can be used for various storage related application such as BIG DATA, etc. The controller proposed in the paper is mainly comprised of some of the basic functionality like read, write operation, refresh, synchronization, etc. The design developed is implemented on FPGA operating on 200MHz clock frequency and coded using verilog language. Xilinx ISE 14.1 is used as a development environment and Modelsim6.3 is used to work on the functional verification of the design.